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Rev: 1.03 2/2000
8/23
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
GS820E32T/Q-150/138/133/117/100/66
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.