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AM42BDS640AGTD9IT Fiches technique(PDF) 3 Page - SPANSION |
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3 / 72 page 2 Am42BDS640AG November 1, 2002 P R E L I M INARY GENERAL DESCRIPTION The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta- neous Read/Write, Burst Mode Flash memory device, orga- nized as 4,194,304 words of 16 bits each. This device uses a single V CC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VID may be used for faster pro- gram performance if desired. The device can also be pro- grammed in standard EPROM programmers. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de- vice provides a burst access of 20 ns at 30 pF with a latency of 95 ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in a 93-ball FBGA package. The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from wait- ing for the completion of program or erase operations. The device is divided as shown in the following table: The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst opera- tions, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. The burst read mode feature gives system designers flexibil- ity in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The ac- tive clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firm- ware from the Flash memory device. The host system can detect whether a program or erase op- eration is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. The sector lock/unlock com- mand sequence disables or re-enables both program and erase operations in any sector. When at V IL, WP# locks sec- tors 0 and 1 (bottom boot device) or sectors 132 and 133 (top boot device). The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Bank Quantity Size A 4 8 Kwords 31 32 Kwords B 32 32 Kwords C 32 32 Kwords D 31 32 Kwords 4 8 Kwords |
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