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AM42BDS640AGTC8IT Fiches technique(PDF) 10 Page - SPANSION

No de pièce AM42BDS640AGTC8IT
Description  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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November 1, 2002
Am42BDS640AG
9
P R E L I M INARY
PIN DESCRIPTION
A19–A0
=
20 Address Inputs (Common)
A21–A20
=
2 Address Inputs (Flash)
DQ15–DQ0
=
16 Data Inputs/Outputs (Common)
CE#f
=
Chip Enable (Flash)
CE1#s
=
Chip Enable 1 (SRAM)
CE2s
=
Chip Enable 2 (SRAM)
OE#
=
Output Enable (Common)
WE#
=
Write Enable (Common)
UB#s
=
Upper Byte Control (SRAM)
LB#s
=
Lower Byte Control (SRAM)
RESET#
=
Hardware Reset Pin, Active Low
VCCf
=
Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage sup-
ply tolerances)
VIOf
=
Input & Output Buffer Power Supply
must be tied to VCCf.
VCCs
=
SRAM Power Supply
VSS
=
Device Ground (Common)
NC
=
Pin Not Connected Internally
RDY
=
Ready output; indicates the status of
the Burst read. Low = data not valid
at expected time. High = data valid.
CLK
=
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
AVD#
=
Address Valid input. Indicates to de-
vice that the valid address is present
on the address inputs (A21–A0).
Low = for asynchronous mode, indi-
cates valid address; for burst mode,
causes starting address to be
latched.
High = device ignores address in-
puts
WP#
=
Hardware write protect input. At V
IL,
disables program and erase func-
tions in the two outermost sectors.
Should be at V
IH for all other condi-
tions.
ACC
=
At V
ID, accelerates programming;
automatically places device in un-
lock bypass mode. At V
IL, locks all
sectors. Should be at V
IH for all other
conditions.
LOGIC SYMBOL
20
16
DQ15–DQ0
A19–A0
CE#f
OE#
WE#
RESET#
UB#s
RDY
WP#
A21–A20
LB#s
ACC
CE1#s
CE2s
AVD#
CLK


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