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18730 Fiches technique(PDF) 26 Page - Freescale Semiconductor, Inc

No de pièce 18730
Description  Power Management IC with Five Power Management IC with Five Power Management IC with Five Power Management IC with Five
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

18730 Fiches technique(HTML) 26 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
26
Freescale Semiconductor
18730
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Ext / Int : Clock Select control 1
1 = External Clock
0 = Internal Clock
2FS : Clock Select control 2
1 = 2FS on
0 = 2FS off
RSTB Sleep : RSTB Sleep Monitor
*1
1 = RSTB SLEEP Monitor off
0 = RSTB SLEEP Monitor on
S_Off_VG : VG Top side transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
VG_Duty[3] : VG Duty Control MSB
1 = VG Duty[3] is high
0 = VG Duty[3] is low
VG_Duty[2] : VG Duty Control Bit 2
1 = VG Duty[2] is high
0 = VG Duty[2] is low
VG_Duty[1] : VG Duty Control Bit1
1 = VG Duty[1] is high
0 = VG Duty[1] is low
VG_Duty[0] : VG Duty Control LSB
1 = VG Duty[0] is high
0 = VG Duty[0] is low
VG is controlled by PFM method. This register can change
the duty by 16 steps.
Refer to Table 15, VG Duty Settings on page 24 for the
correspondence between the VG Duty maximum values and
register settings.
VO1_V[6] : Reference DAC MSB
1 = VO1_V[6] on
0 = VO1_V[6] off
VO1_V[5] : Reference DAC Bit5
1 = VO1_V[5] on
0 = VO1_V[5] off
VO1_V[4] : Reference DAC Bit4
1 = VO1_V[4] on
0 = VO1_V[4] off
VO1_V[3] : Reference DAC Bit3
1 = VO1_V[3] on
0 = VO1_V[3] off
VO1_V[2] : Reference DAC Bit2
1 = VO1_V[2] on
0 = VO1_V[2] off
VO1_V[1] : Reference DAC Bit1
1 = VO1_V[1] on
0 = VO1_V[1] off
VO1_V[0]: Reference DAC LSB
1 = VO1_V[0] on
0 = VO1_V[0] off
S_Off_VO1 : DDC1 Top side (Ni_mh) / Bottom side
(Li_ion) transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
Refer to Table 10, Output Voltage of VO1 on page 19 for
the correspondence between the output voltage and register
settings.
Table 19. Clock Select Register
0010
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
Ext/Int
Half Freq
RSTB sleep
S_Off_VG
VG_Duty [3]
VG_Duty[2]
VG_Duty[1]
VG_Duty[0]
Default
0
0
1
0
0
0
0
0
Table 20. VO1 Output Voltage Register
0011
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
VO1_V[6]
VO1_V[5]
VO1_V[4]
VO1_V[3]
VO1_V[2]
VO1_V[1]
VO1_V[0]
S_Off_VO1
Default
1
0
0
0
0
0
0
0


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