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HCPL-193K Fiches technique(PDF) 5 Page - Agilent(Hewlett-Packard)

No de pièce HCPL-193K
Description  Dual Channel Line Receiver Dual Channel Line Receiver Dual Channel Line Receiver
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Fabricant  HP [Agilent(Hewlett-Packard)]
Site Internet  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HCPL-193K Fiches technique(HTML) 5 Page - Agilent(Hewlett-Packard)

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5
Absolute Maximum Ratings
Storage Temperature ................................................. -65
°C to +150°C
Operating Temperature ............................................... -55
°C to +125°C
Lead Solder Temperature ................................................ 260
°C for 10 s
1.6 mm below seating plane
Forward Input Current – II (each channel) ................................. 60 mA2
Reverse Input Current ................................................................. 60 mA
Supply Voltage – VCC ....................................... 7 V (1 Minute Maximum)
Enable Input Voltage – VE (each channel) ...................................... 5.5 V
Not to exceed VCC by more than 500 mV
Output Collector Current – IO (each channel) ............................. 25 mA
Output Collector Power Dissipation (each channel) ................... 40 mW
Output Collector Voltage – VO (each channel) ................................... 7 V
Total Package Power Dissipation .............................................. 564 mW
Input Power Dissipation (each channel) ................................... 168 mW
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
IIL
0
250
µA
Input Current, High Level*
IIH
12.5
60
mA
Supply Voltage, Output
VCC
4.5
5.5
V
High Level Enable Voltage
VEH
2.0
VCC
V
Low Level Enable Voltage
VEL
0
0.8
V
Fan Out (@ RL = 4 kΩ)
N
5
TTL
Loads
Operating Temperature
TA
-55
125
°C
*12.5 mA condition permits at least 20% guardband for optical coupling variation. Initial
switching threshold is 10 mA or less.
Recommended Operating Conditions
ESD Classification
(MIL-STD-883, Method 3015) .............................................. (
∆), Class 1
Schematic
A 0.1
µF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN
PINS 10 AND 15 (SEE NOTE 1).


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