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AM45DL3208GB85IT Fiches technique(PDF) 10 Page - Advanced Micro Devices |
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AM45DL3208GB85IT Fiches technique(HTML) 10 Page - Advanced Micro Devices |
10 / 66 page 8 Am45DL3208G March 12, 2004 PR EL I M I N ARY PIN DESCRIPTION A18–A0 = 19 Address Inputs (Common) A20–A19, A-1 = 3 Address Inputs (Flash) SA = Lowest Order Address Pin (PSRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#1s = Chip Enable 1 (PSRAM) CE2s = Chip Enable 2 (PSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (PSRAM) LB#s = Lower Byte Control (PSRAM) CIOf = I/O Configuration (Flash) CIOf = V IH = Word mode (x16), CIOf = V IL = Byte mode (x8) CIOs = I/O Configuration (PSRAM) CIOs = V IH = Word mode (x16), CIOs = V IL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) V CCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CCs = PSRAM Power Supply V SS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 19 16 or 8 DQ15–DQ0 A18–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A20–A19, A-1 LB#s CIOf CIOs CE1#s CE2s |
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