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CH5101A Datasheet(Fiches technique) 5 Page - List of Unclassifed Manufacturers

Numéro de pièce CH5101A
Description  CMOS Monochrome Digital Video Camera
Télécharger  32 Pages
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Fabricant  ETC1 [List of Unclassifed Manufacturers]
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CHRONTEL
CH5101A
201-0000-033 Rev 1.0, 6/2/99
5
Table 1. Pin Descriptions
Note: Pin numbers in parenthesis ( ) are for 52 pin PQFP
Pin
Type
Symbol
Description
21-14
(14-7)
Out
Y[7:0]
Video Output
Provides the luminance data of the digital video output.
1,7,11,22,34,
(4,15,27,46,52)
Power
DVDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH5101.
4,8,24,36,
(1, 17, 29, 49)
Power
DGND
Digital Ground
Provides the ground reference for the digital section of CH5101. These
pins MUST be connected to the system ground.
31-25
(24-18)
In
PUD[5:0]*
PUD[6]
Power Up Detect (internal pull-up)
These are inputs controlling the default value of IIC register bits
M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low.
NOTE: PUD[5:0]* are logically inverted
23
(16)
Out
CLKOUT
Video Pixel Clock Output
This pin outputs a buffered clock signal which can be used to latch data
output by pins Y[7:0]
9
(2)
Out
VS*
Vertical Sync Output (active low)
Outputs a vertical sync pulse.
10
(3)
Out
HS*
Horizontal Sync Output (active low)
Outputs a horizontal sync pulse.
12
(5)
Out
OVR
Over Range
This pin is high when the A/D converter input is beyond the full scale
range of the A/D.
13
(6)
Out
HREF
Horizontal Reference
Active video timing signal. This output is high when active data is being
output from the device, and low otherwise.
6
(51)
In
SC
Serial Clock
IIC clock input pin.
5
(50)
In/Out
SD
Serial Data
IIC data input/output pin.
2
(47)
In
AS
Chip Address Select (internal pullup)
This pin selects the IIC address for the device.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
3
(48)
In
RESET*
Chip Reset (active low, internal pullup)
Puts all registers into power-on default states. The state at pin SD must
be HIGH during reset for proper initialization.
38
(31)
In/Out
XO
Crystal Output
A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached
between XO and XI/FIN.
39
(32)
In
XI/FIN
Crystal Input or External input
A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached
between XO and XI/FIN. An external CMOS compatible clock can be
connected to XI/FIN as an alternative.




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