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LFECP3E-5F672I Fiches technique(PDF) 11 Page - Lattice Semiconductor |
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LFECP3E-5F672I Fiches technique(HTML) 11 Page - Lattice Semiconductor |
11 / 117 page 2-8 Architecture Lattice Semiconductor LatticeECP/EC Family Data Sheet Secondary Clock Sources LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7. Figure 2-7. Secondary Clock Sources Clock Routing The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-10. 20 Secondary Clock Sources To Quadrant Clock Selection From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing |
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