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LFECP33E-5T144I Fiches technique(PDF) 6 Page - Lattice Semiconductor

No de pièce LFECP33E-5T144I
Description  LatticeECP/EC Family Data Sheet
Download  117 Pages
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Fabricant  LATTICE [Lattice Semiconductor]
Site Internet  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFECP33E-5T144I Fiches technique(HTML) 6 Page - Lattice Semiconductor

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2-3
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D


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