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AM93LC86INA Fiches technique(PDF) 9 Page - Anachip Corp |
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AM93LC86INA Fiches technique(HTML) 9 Page - Anachip Corp |
9 / 12 page AM93LC86 16384-bits Serial Electrically Erasable PROM (Preliminary) Anachip Corp. www.anachip.com.tw Rev 0.1 Oct 20, 2003 9/12 Pin Description (Continued) Chip select (CS) A high level selects the device. A low level deselects the device an forces it into standby mode. However, a programming cycle which is already initiated will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. Serial clock (SK) The serial clock is used to synchronize the communication between a master device and the AM93LC86. Opcode, address, and data bits are clocked in on the positive edge of SK. Data bits are also clocked out on the positive edge of SK. SK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. SK is a “don’t care” if CS is low (device deselected). If CS is high, but START condition has not been detected, any number of clock cycles can be recevived by the device without changing its status (i.e., waiting for START condition). SK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycles. After detection of a start condition the specified number of clock cycles (respectively low to high transitions of SK) must be provided. These clock cycles are required to clock in all opcode, address, and data bits before an instruction is executed (see the table of instruction set). SK and DI then become don’t care inputs waiting for a new start condition to be detected. Note: CS must go low between consecutive instructions, except when performing a sequential read. Data input (DI) Data input is used to clock in a start bit, opcode, address, and data synchronously with the CLK input. Data output (DO) Data output is used in the READ mode to output data synchronously with the CLK input( TPD after the positive edge of CLK) Write protection ( WP ) This pin allows the user to enable or disable the ability to write data to the memory array. If the WP pin is floated or tied to VCC, the device can be programmed. If the WP pin is tied to GND, programming will be inhibited. There is an internal pull-up on this device that enables programming if this pin is left floating. Organization (ORG) When ORG is connected to VCC, the X16 memory organization is selected. When ORG is tied to GND, the X8 memory organization is selected. There is an internal pull-up resistor on the ORG pin that will select X16 organization when left unconnected. |
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