MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–202

REV 5

3/93

High Speed Dual Type D

Master-Slave Flip-Flop

The MC10231 is a dual master–slave type D flip–flop. Asynchronous Set (S)

and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop

may be clocked separately by holding the common clock in the low state and

using the enable inputs for the clocking function. If the common clock is to be

used to clock the flip–flop, the Clock Enable inputs must be in the low state. In

this case, the enable inputs perform the function of controlling the common

clock.

The output states of the flip–flop change on the positive transition of the

clock. A change in the information present at the data (D) input will not affect the

output information at any other time due to master–slave construction.

PD = 270 mW typ/pkg (No Load)

tpd = 2 ns typ

tTog= 225 MHz typ

tr, tf = 2.0 ns typ (20%–80%)

R2 13

LOGIC DIAGRAM

VCC1 = PIN 1

VCC2 = PIN 16

VEE = PIN 8

S1 5

D1 7

CE1 6

R1 4

CC 9

CE2 11

D2 10

S2 12

Q1

Q1

Q2

Q2

2

3

15

14

CLOCKED TRUTH TABLE

R–S TRUTH TABLE

C

D

Qn+1

R

S

Qn+1

L

X

Qn

L

L

Qn

H

L

L

L

H

H

H

H

H

H

L

L

C = CE + CC. A clock H is a clock

transition from a low to a high state.

H

H

N.D.

N.D. = Not Defined

MC10231

DIP

PIN ASSIGNMENT

VCC1

Q1

Q1

R1

S1

CE1

D1

VEE

VCC2

Q2

Q2

R2

S2

CE2

D2

CC

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02