MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–126

REV 5

3/93

Quint Latch

The MC10175 is a high speed, low power quint latch. It features five D type

latches with common reset and a common two–input clock. Data is transferred

on the negative edge of the clock and latched on the positive edge. The two

clock inputs are “OR”ed together.

Any change on the data input will be reflected at the outputs while the clock

is low. The outputs are latched on the positive transition of the clock. While the

clock is in the high state, a change in the information present at the data inputs

will not affect the output information. The reset input is enabled only when the

clock is in the high state.

PD = 400 mW typ/pkg (No Load)

tpd = 2.5 ns typ (Data to Output)

tr, tf = 2.0 ns typ (20%–80%)

LOGIC DIAGRAM

VCC1 = PIN 1

VCC2 = PIN 16

VEE = PIN 8

10

14

D

C

Q

R

6

7

11

D

C

Q

R

D

C

Q

R

D

C

Q

R

D

C

Q

R

15

3

4

12

9

5

13

D0

C0

C1

RESET

D1

D3

D4

D2

2

Q0

Q1

Q3

Q4

Q2

TRUTH TABLE

D

C0

C1

Reset

Qn+1

L

L

L

X

L

H

L

L

X

H

X

H

X

L

Q n

X

X

H

L

Q n

X

H

X

H

L

X

X

H

H

L

MC10175

DIP

PIN ASSIGNMENT

VCC1

Q2

Q3

Q4

D4

C0

C1

VEE

VCC2

Q1

Q0

D2

D1

RESET

D0

D3

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).