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MC100ES6039EGR2 Fiches technique(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC100ES6039EGR2 Fiches technique(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 8 page Advanced Clock Drivers Device Data 2 Freescale Semiconductor MC100ES6039 Figure 1. 20-Lead Pinout (Top View) CLK CLK MR VCC 17 18 16 15 14 13 12 4 3 56 7 8 9 Q0 11 10 Q1 Q1 Q2 Q2 Q3 Q3 VEE EN 19 20 2 1 VCC Q0 VBB VCC NC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 1. Pin Description Pin Function CLK(1), CLK(1) 1. Pins will default low when left open. ECL Diff Clock Inputs EN(1) ECL Sync Enable MR(1) ECL Master Reset VBB ECL Reference Output Q0, Q1, Q0, Q1 ECL Diff ÷2/4 Outputs Q2, Q3, Q2, Q3 ECL Diff ÷4/6 Outputs DIVSELa(1) ECL Freq. Select Input ÷2/4 DIVSELb(1) ECL Freq. Select Input ÷4/6 VCC ECL Positive Supply VEE ECL Negative Supply NC No Connect Table 2. Function Tables CLK EN MR Function Z ZZ X L H X L L H Divide Hold Q0:3 Reset Q0:3 X = Don’t Care Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa Q0:1 Outputs L H Divide by 2 Divide by 4 DIVSELb Q2:3 Outputs L H Divide by 4 Divide by 6 Figure 2. Logic Diagram CLK CLK EN MR ÷2/4 Q0 Q0 Q1 Q1 ÷4/6 Q2 Q2 Q3 Q3 R R DIVSELa DIVSELb VEE |
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