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Revision 1.1
Jan.
2004
4
R0201-
STC62WV12816
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
(Vcc = 2.7~5.5V)
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
ELQV
t
ACS
Chip Select Access Time
(CE)
--
--
55
--
--
70
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
----
30
----
35
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
E1LQX
t
CLZ
Chip Select to Output Low Z
(CE)
10
--
--
10
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,UB)
10
----
10
----
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
----5
----
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE)
--
--
30
--
--
35
ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB,UB)
--
--
30
--
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW V
CC DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
t CDR
Vcc
t R
VIH
VIH
Vcc
VDR
1.5V
≥
CE
Vcc - 0.2V
≥
STC
STC62WV12816
(1)
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
NOTE :
MIN. TYP. MAX.
MIN. TYP. MAX.
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
CYCLE TIME : 70ns