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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS63810 Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS63810 Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 41 page  7 TPS63810 www.ti.com SLVSEK4 – JULY 2019 Product Folder Links: TPS63810 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Timing Requirements (continued) Over operating junction temperature range and recommended supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tVD;ACK Data valid acknowledge time Standard mode 3.45 µs Fast mode 0.9 Fast mode plus 0.45 Cb Capacitive load for each bus line Standard mode 400 Fast mode 400 Fast mode plus 550 tw(VSEL) VSEL pulse duration VSEL = high or low 5 µs 6.7 Switching Characteristics Over operating junction temperature range and recommended input voltage range (unless otherwise noted). Typical values are at VI = 3.6 V, VO = 3.3 V, and TJ = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(EN) Delay between a rising edge on the EN pin and the start of the output voltage ramp TJ = 25°C, VI = 3.6 V 229 440 µs td(PG) Power-good delay VO falling 50 µs SR Slew rate of internal ramp during dynamic voltage scaling SLEW = 00b, forced-PWM operation ±1 V/ms SLEW = 01b, forced-PWM operation ±2.5 SLEW = 10b, forced-PWM operation ±5 SLEW = 11b, forced-PWM operation ±10 Switching frequency PWM operation, IO = 100 mA 0.5 3.1 MHz td(VSEL) Delay between rising edge of VSEL and start of DVS ramp Measured from rising edge of VSEL to start of ramp. 5 µs |
Numéro de pièce similaire - TPS63810 |
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Description similaire - TPS63810 |
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