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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TLV320ADC6140 Fiches technique(PDF) 85 Page - Texas Instruments |
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TLV320ADC6140 Fiches technique(HTML) 85 Page - Texas Instruments |
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85 / 122 page  85 TLV320ADC6140 www.ti.com SBAS992 – JULY 2019 Product Folder Links: TLV320ADC6140 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table 99. CH3_CFG0 Register Field Descriptions (continued) Bit Field Type Reset Description 6-5 CH3_INSRC[1:0] R/W 0h Channel 3 input configuration. 0d = Analog differential input (the GPI3 and GPO3 pin functions must be disabled) 1d = Analog single-ended input (the GPI3 and GPO3 pin functions must be disabled) 2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN2 and PDMCLK) 3d = Reserved 4 CH3_DC R/W 0h Channel 3 input coupling (applicable for the analog input). 0d = AC-coupled input 1d = DC-coupled input 3-2 CH3_IMP[1:0] R/W 0h Channel 3 input impedance (applicable for the analog input). 0d = Typical 2.5-kΩ input impedance 1d = Typical 10-kΩ input impedance 2d = Typical 20-kΩ input impedance 3d = Reserved 1 Reserved R 0h Reserved 0 CH3_DREEN R/W 0h Channel 3 dynamic range enhancer (DRE) and automatic gain controller (AGC) setting. 0d = DRE and AGC disabled 1d = DRE or AGC enabled based on the configuration of bit 3 in register 108 (P0_R108) 8.6.1.1.47 CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h] This register is configuration register 1 for channel 3. Figure 133. CH3_CFG1 Register 7 6 5 4 3 2 1 0 CH3_GAIN[5:0] Reserved R/W-0h R-0h Table 100. CH3_CFG1 Register Field Descriptions Bit Field Type Reset Description 7-2 CH3_GAIN[5:0] R/W 0h Channel 3 gain. 0d = Channel gain is set to 0 dB 1d = Channel gain is set to 1 dB 2d = Channel gain is set to 2 dB 3d to 41d = Channel gain is set as per configuration 42d = Channel gain is set to 42 dB 43d to 63d = Reserved 1-0 Reserved R 0h Reserved 8.6.1.1.48 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h] This register is configuration register 2 for channel 3. Figure 134. CH3_CFG2 Register 7 6 5 4 3 2 1 0 CH3_DVOL[7:0] R/W-C9h |
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