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TLV320ADC6140 Fiches technique(PDF) 52 Page - Texas Instruments |
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TLV320ADC6140 Fiches technique(HTML) 52 Page - Texas Instruments |
52 / 122 page D1[n] D2[n] D1[n+1] D2[n+1] D1[n+2] PDMCLK PDMDINx Mic-1 Data Mic-2 Data (n+1) th Sample n th Sample (n+2) th Sample Mic-1 Data Mic-2 Data Mic-1 Data VDD Digital PDM Microphone U1 DATA CLK GND VDD SEL Digital PDM Microphone U2 DATA CLK GND VDD SEL VDD TLV320ADCx140 IOVDD VDD GPIx (PDMDINx) GPOx (PDMCLK) GND GND 52 TLV320ADC6140 SBAS992 – JULY 2019 www.ti.com Product Folder Links: TLV320ADC6140 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 8.3.9 Digital PDM Microphone Record Channel In addition to supporting analog microphones, the device also interfaces to digital pulse-density-modulation (PDM) microphones and uses high-order and high-performance decimation filters to generate pulse code modulation (PCM) output data that can be transmitted on the audio serial interface to the host. If analog microphones are not used in the system, then the analog input pins (INxP and INxM) can be repurposed as the GPIx and GPOx pins respectively and can be configured for the PDMDINx and PDMCLK clocks for digital PDM microphone recording. The device supports up to eight digital microphone recording channels. The device internally generates PCMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz, 1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz, 2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz) using the PDMCLK_DIV[1:0], P0_R31_D[1:0] register bits. PDMCLK can be routed on the GPOx pin. This clock can be connected to the external digital microphone device. Figure 78 shows a connection diagram of the digital PDM microphones. Figure 78. Digital PDM Microphones Connection Diagram to the TLV320ADC6140 The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK. Internally, the device latches the steady value of the data on the rising edge of PDMCLK or the falling edge of PDMCLK based on the configuration register bits set in P0_R32_D[7:4]. Figure 79 shows the digital PDM microphone interface timing diagram. Figure 79. Digital PDM Microphone Protocol Timing Diagram When the digital microphone is used for recording, the analog blocks of the respective ADC channel are powered down and bypassed for power efficiency. Use the CH1_INSRC[1:0] (P0_R60_D[6:5]), CH2_INSRC[1:0] (P0_R65_D[6:5]), CH3_INSRC[1:0] (P0_R70_D[6:5]), and CH4_INSRC[1:0] (P0_R75_D[6:5]) register bits to select the analog microphone or digital microphone for channel 1 to channel 4. |
Numéro de pièce similaire - TLV320ADC6140 |
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Description similaire - TLV320ADC6140 |
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