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TLA2518 Fiches technique(PDF) 28 Page - Texas Instruments |
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TLA2518 Fiches technique(HTML) 28 Page - Texas Instruments |
28 / 32 page AIN/GPIO SCLK SDI AVDD DECAP 28 TLA2518 SBAS980 – JUNE 2019 www.ti.com Product Folder Links: TLA2518 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines Figure 33 shows a board layout example for the TLA2518. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the AVDD supply away from noise sources. Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference voltage for the TLA2518. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins and connect CREF to the device pins with thick copper tracks. 10.2 Layout Example Figure 33. Example Layout |
Numéro de pièce similaire - TLA2518 |
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Description similaire - TLA2518 |
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