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CDCE6214-Q1 Fiches technique(PDF) 13 Page - Texas Instruments

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No de pièce CDCE6214-Q1
Description  CDCE6214-Q1 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
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CDCE6214-Q1 Fiches technique(HTML) 13 Page - Texas Instruments

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CDCE6214-Q1
www.ti.com
SNAS786 – AUGUST 2019
Product Folder Links: CDCE6214-Q1
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Copyright © 2019, Texas Instruments Incorporated
Feature Description (continued)
The reference MUX selects the reference clock for the PLL. Pin 4 (REFSEL) can be used to select PRIREF or
SECREF Input path. Alternatively, this can be configured through the register settings.
A reference divider or a clock doubler can be engaged to further multiply (2x) or divide the reference clock to the
PLL.
The output clock from the reference block can be bypassed to the OUT0 and other output channels. The
bypassed clock is selectable between the Input clock or PFD clock.
8.3.1.2 XTAL Oscillator
The SECREF_P and SECREF_N pins provide a crystal oscillator stage to drive a fundamental mode crystal in
the range of 10 MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF. The
drive capability of the oscillator is adjusted using register programming.
8.3.1.3 LVCMOS
The LVCMOS input buffer threshold voltage follows VDD_REF. This allows the engineer to use the device as a
level shifter because the outputs all have separate supplies.
8.3.1.4 Differential AC-Coupled
The differential input stage has an internal bias generator and internal AC-coupling capacitor. It should only be
used as an AC-coupled reference input.
8.3.1.5 Reference MUX
Either PRIREF or SECREF can be selected as clock to the PLL and clock distribution path. The reference MUX
is controlled either through pin 4 (REFSEL) or through the register settings.
8.3.1.6 Reference Divider
A reference divider can be used to divide higher input frequencies to the permitted PFD range. It supports
division values of 1 to 255.
8.3.1.7 Reference Doubler
The reference path contains a doubler circuit. It is used to double the input frequency and can be used to
achieve the highest PFD update frequency of 100 MHz using a 50-MHz crystal or PFD update frequency of 50
MHz using a 25-MHz crystal.
8.3.1.8 Clock Bypass
The input reference clock or the PFD clock can be bypassed to OUT0 (LVCMOS output). It can also be
bypassed to the OUT1–OUT4 pins, which are selectable among other clock distribution networks.
8.3.2 Phase-Locked Loop (PLL)
The CDCE6214-Q1 has a fully integrated Phase-Locked Loop (PLL) circuit. The error between a reference
phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is
fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop
filter tunes an internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a feedback
divider (N-counter) back to the PFD.
Integer and Fractional-N PLL mode of operation.
24-bit Numerator and Denominator can be used to generate fractional frequencies with frequency accuracy
better than 0.1ppm.
PFD operates between 1 MHz and 100 MHz.
Live Lock Detector provides PLL Lock status (not in SSC mode). Additionally, sticky bit lock detect detects if
there was any temporary loss of lock.
Integrated selectable loop filter components.
For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize


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