TLC3541, TLC3545

SLAS345 − DECEMBER 2001

11

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PRINCIPLES OF OPERATION

control and timing

device initialization/RESET cycle

The TLC3541/45 each require one RESET cycle after power-on for initialization in order to operate properly.

The RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK

falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS

high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is 3FC0h.

This output code is useful in determining when a valid reset/initialization has occurred.

The TLC3541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by

asserting FS low if CS is already asserted low. The RESET cycle can be terminated by either asserting CS high

(as shown in the first RESET cycle in Figure 14), or by asserting FS high (as shown in the second RESET cycle

in Figure 14), whichever happens first.

1−8 Falling SCLK Edges−

ADC is Initialized

1

2

1

4

8

MSB

LSB+1

1

2

8

1

4

16

LSB

1111−1111−0000−00−XX

tcyc(reset)

SCLK

OR

tcyc(reset)

FS High for Valid Initialization

Normal Cycle−Sample

and Convert

t(PWRDWN)

SDO Data−Reset of Previous Cycle’s Sample

For TLC35xx−LSB Presented on 14th Rising SCLK Edge

Normal Cycle−Sample

and Convert

CS

FS

SDO

Figure 14. TLC3541/45 Initialization Timing

sampling

The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal

on the CS input (or FS input for the TLC3541.)

conversion

Each device completes a conversion in the following manner. The conversion is started after the 24th falling

SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion

cycle. The conversion takes a maximum of 2.67

µs to complete. Enough time (for conversion) should be allowed

before the next falling edge on the CS input (or rising edge on the FS input for the TLC3541) so that no

conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO

during the following cycle is 3FC0h. This predefined output code is helpful in determining if the cycle time is not

long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid.

For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during

the previous cycle. The output data format is shown in the following table.

SERIAL OUTPUT DATA FORMAT

MSB [D15:D2]

LSB [D1:D0]

TLC3541/45

Conversion result (OD13−OD0)

Don’t care