4.0

4.1.

Storage temperature range ........................................................... -65

C to +150C

C

Lead temperature (soldering, 60 seconds) .................................. +300

C

Thermal resistance, junction-to-case (

Thermal resistance, junction-to-ambient (

ESD Sensitivity (HBM)………………………………………………... Class 2

4.2.

)……………………….… -55

C to +125C

4.3.

Jitter

Peak-to-Peak.............................................................................. 800ps

RMS............................................................................................ 190ps

Capacitance (Input-to-Output) ....................................................... 14pF 6/

Input Capacitance .......................................................................... 4pF 7/

Maximum Continuous Working Voltage ......................................... 100 Vpeak 9/ 10/

4.4. Radiation Features

Maximum total dose available (dose rate = 50

– 300 rads(Si)/s)…… 50k rads(Si)

Single event phenomenon (SEP):

No single event latchup (SEL) occurs at effective linear energy

trans

fer (LET): ………………...……………………. ≤ 80MeV-cm2/mg 8/

1/ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to

absolute maximum ratings for extended periods may affect device reliability.

2/ VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.

3/ Measurement taken under absolute worst case condition and represent data taken with thermal camera for highest power density location. See MIL-STD-

1835 for average

ΘJC number.

4

/ All typical specifications are at TA = 25°C, 3.6 V ≤ VDD1 ≤ 5. V, 3.3 V ≤ VDD2 ≤ 5.0 V, unless otherwise noted. Switching specifications are tested with

CL = 15 pF and CMOS signal levels, unless otherwise noted.

common-mode voltage edges.

6/ The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.

7/ Input capacitance is from any input data pin to ground.

8/ Limits are characterized at initial qualification and after any design or process changes that may affect the SEP characteristics, but are not production lot