Moteur de recherche de fiches techniques de composants électroniques
Nom de la pièce
ADUCM330WFS Datasheet(Fiches technique) 11 Page - Analog Devices
Numéro de pièce
AD [Analog Devices]
Rev. A | Page 11 of 17
= −40°C to +115°C
= +115°C to +125°C
Channel 1 (ADC1)
Voltage ADC (VADC)
Reduction from 1% to 3% mode
Guaranteed by design, but not production tested.
Valid for PGA current ADC gain settings of 4, 8, 16, 32, and 64.
These specifications include temperature drift.
A system calibration removes this error at a given temperature (and at a given gain for the current channel).
The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of
the temperature drift characterization data distribution.
Includes internal reference temperature drift.
The gain drift is included in the total gain error. This parameter is an indicator of the gain error due to the temperature drift in the ADC. The typical value of this
parameter is the mean of the temperature drift characterization data distribution.
For data rates of 4 kHz and 8 kHz with a PGA gain = 32 or greater, allow 10 ms settling time after ADC Current Channel 0 (ADC0) wakes up from power-down mode.
Voltage channel specifications include resistive attenuator input stage, unless otherwise stated.
RMS noise is referred to voltage attenuator input. For example, at an ADC data output frequency (f
) = 1 kHz, the typical rms noise at the ADC input is 7.5 µV. Scaling
by the attenuator (1:24) yields these input referred noise figures.
Valid after an initial self calibration.
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
Valid for a differential input less than 10 mV.
The reference voltage, V
, for the ADC is provided by the signal pair, AVDD18 and GND_SW.
The absolute value of the voltage of VTEMP and GND_SW must be 100 mV (minimum) for accurate operation of the temperature ADC (T
Measured using box method.
The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
Valid after an initial self gain calibration.
Endurance is qualified to 10,000 cycles, as per JEDEC Standard 22 Method A117 and measured at −40°C, +25 °C, and +115°C. Typical endurance at 25°C is 100,000 cycles.
Data retention lifetime equivalent at junction temperature (T
) = 85°C, as per JEDEC Standard 22 Method A117. Data retention lifetime derates with junction temperature.
Measured with LIN communication active.
Not production tested but are supported by LIN compliance testing.
Typical additional supply current consumed during Flash/EE memory programming is 3 mA, and typical additional supply current consumed during erase cycles is 1 mA.
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