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ADRF5730 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce ADRF5730
Description  Silicon Digital Attenuator
Download  19 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADRF5730 Fiches technique(HTML) 4 Page - Analog Devices

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ADRF5730
Data Sheet
Rev. 0 | Page 4 of 19
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Step Error
Between any successive state
With Impedance Match
See Figure 44
100 MHz to 10 GHz
±0.11
dB
10 GHz to 18 GHz
±0.18
dB
18 GHz to 26 GHz
±0.23
dB
26 GHz to 35 GHz
±0.3
dB
35 GHz to 40 GHz
±0.51
dB
Without Impedance Match
See Figure 43
100 MHz to 10 GHz
±0.11
dB
10 GHz to 18 GHz
±0.19
dB
18 GHz to 26 GHz
±0.23
dB
26 GHz to 35 GHz
±0.26
dB
35 GHz to 40 GHz
±0.65
dB
RELATIVE PHASE
Referenced to insertion loss
With Impedance Match
See Figure 44
10 GHz
15
Degrees
18 GHz
30
Degrees
26 GHz
50
Degrees
35 GHz
75
Degrees
40 GHz
100
Degrees
Without Impedance Match
See Figure 43
10 GHz
15
Degrees
18 GHz
30
Degrees
26 GHz
50
Degrees
35 GHz
75
Degrees
40 GHz
110
Degrees
SWITCHING CHARACTERISTICS
All attenuation states at input power = 10 dBm
Rise and Fall Time (tRISE and tFALL)
10% to 90% of RF output
35
ns
On and Off Time (tON and tOFF)
50% triggered control (CTL) to 90% of RF output
125
ns
RF Amplitude Settling Time
0.1 dB
50% triggered CTL to 0.1 dB of final RF output
250
ns
0.05 dB
50% triggered CTL to 0.05 dB of final RF output
350
ns
Overshoot
1
dB
Undershoot
−2.5
dB
RF Phase Settling Time
f = 5 GHz
50% triggered CTL to 5° of final RF output
160
ns
50% triggered CTL to 1° of final RF output
180
ns
INPUT LINEARITY1
100 MHz to 30 GHz
0.1 dB Power Compression (P0.1dB)
Insertion Loss State
30
dBm
Other Attenuation States
27
dBm
Third-Order Intercept (IP3)
Two-tone input power = 14 dBm per tone,
Δf = 1 MHz, all attenuation states
50
dBm
DIGITAL CONTROL INPUTS
LE, PS, D0, D1, D2, D3/SEROUT,2 D4/SERIN,
D5/CLK pins
Voltage
Low (VINL)
0
0.8
V
High (VINH)
1.2
3.3
V
Current
Low (IINL)
<1
µA
High (IINH)
D0, D1, D2
33
µA
LE, PS, D3/SEROUT2, D4/SERIN, D5/CLK pins
<1
µA


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