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ADPA7001CHIPS Datasheet(Fiches technique) 6 Page - Analog Devices

Numéro de pièce ADPA7001CHIPS
Description  Wideband Power Amplifier
Télécharger  18 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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ADPA7001CHIPS
Data Sheet
Rev. A | Page 6 of 18
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
3
4
5
6
8
7
16
1
RFIN
RFOUT
ADPA7001CHIPS
15
14 13
12
11 10 9
Figure 2. Pad Configuration
Table 6. Pad Function Descriptions
Pad No.
Mnemonic
Description
1
RFIN
RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
2
VGG12A
Gate Control Pad for the First and Second Stage Amplifiers. See Figure 4 for the interface schematic.
3, 4
VDD1A,
VDD2A
Drain Bias Voltage Pads for the First and Second Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 µF, and
4.7 µF are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic.
5
VGG34A
Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure 4 for the interface schematic.
6, 7
VDD3A,
VDD4A
Drain Bias Voltage Pads for the Third and Fourth Stage Amplifiers. External bypass capacitors of 100 pF, 0.1 µF, and
4.7 µF are required on these pads. Connect these pads to a 3.5 V supply. See Figure 5 for the interface schematic.
8
RFOUT
RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic.
9
VDET
DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through an
external resistor. See Figure 9 for the interface schematic.
10
VREF
DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature
compensation of VDET. See Figure 10 for the interface schematic.
11, 12
VDD4B,
VDD3B
Drain Bias Voltage Pads for the Fourth and Third Stage Alternative Bias Configuration. External bypass
capacitors of 100 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic.
13
VGG34B
Gate Control Pad for the Third and Fourth Stage Alternative Bias Configuration. Coupling capacitors are
required. See Figure 8 for the interface schematic.
14, 15
VDD2B,
VDD1B
Drain Bias Voltage Pads for the Second and First Stage Alternative Bias Configuration. External bypass
capacitors of 100 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic.
16
VGG12B
Gate Control Pad for the First and Second Stage Alternative Bias Configuration. Coupling capacitors are
required. See Figure 8 for the interface schematic.
Die Bottom
GND
Ground. Die bottom must be connected to RF/dc ground. See Figure 6 for the interface schematic.




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