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CD74HC4017NSR Fiches technique(PDF) 1 Page - Texas Instruments |
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CD74HC4017NSR Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 14 page 1 Data sheet acquired from Harris Semiconductor SCHS200D Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC =5V, CL = 15pF, TA =25 oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Description The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes from high to low, and can be used in conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except “0”, low. The device can drive up to 10 low power Schottky equivalent loads. Pinout CD54HC4017 (CERDIP) CD74HC4017 (PDIP, SOIC, SOP, TSSOP) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC4017F3A -55 to 125 16 Ld CERDIP CD74HC4017E -55 to 125 16 Ld PDIP CD74HC4017M -55 to 125 16 Ld SOIC CD74HC4017MT -55 to 125 16 Ld SOIC CD74HC4017M96 -55 to 125 16 Ld SOIC CD74HC4017NSR -55 to 125 16 Ld SOP CD74HC4017PW -55 to 125 16 Ld TSSOP CD74HC4017PWR -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 5 1 0 2 6 7 GND 3 VCC CP CE TC 9 4 8 MR November 1997 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC4017, CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs [ /Title (CD74 HC401 7) /Sub- ject (High Speed CMOS Logic Decade Counte |
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