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ADV202-SD-EB Fiches technique(PDF) 10 Page - Analog Devices |
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ADV202-SD-EB Fiches technique(HTML) 10 Page - Analog Devices |
10 / 40 page ADV202 Rev. 0 | Page 10 of 40 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter Description Min Typ Max Unit DREQPULSE DREQ Pulse Width1 1 15 JCLK cycles2 t DREQ DACK Assert to Subsequent DREQ Delay 2.5 3.5 × JCLK + 7.5 ns JCLK cycles t RDSU RD to DACK Setup 0 ns t RD DACK to Data Valid 2.5 11 ns tHD Data Hold 1.5 ns DACKLO DACK Assert Pulse Width 2 JCLK cycles DACKHI DACK Deassert Pulse Width 2 JCLK cycles t RDHD RD Hold after DACK Deassert 0 ns RDFSRQ RD Assert to FSRQ Deassert (FIFO Empty) 1.5 2.5 × JCLK + 7.5 ns JCLK cycles t DREQRTN DACK to DREQ Deassert (DR × PULS = 0) 2.5 3.5 × JCLK + 7.5 ns JCLK cycles 1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. 2 For a definition of JCLK, see the section. PLL RD DACK DREQ HDATA 0 1 2 tRD tHD DREQPULSE tDREQ tRDSU tRDHD DACKHI DACKLO Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000) RD DACK DREQ HDATA 0 1 2 tRD tHD tDREQRTN tRDSU tRDHD DACKHI DACKLO Figure 10. Single Read forDREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) |
Numéro de pièce similaire - ADV202-SD-EB |
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Description similaire - ADV202-SD-EB |
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