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GD25LE64C Fiches technique(PDF) 5 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LE64C Fiches technique(HTML) 5 Page - GigaDevice Semiconductor (Beijing) Inc. |
5 / 79 page 1.8V Uniform Sector Dual and Quad Serial Flash GD25LE64C 5 2. GENERAL DESCRIPTION The GD25LE64C (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s. CONNECTION DIAGRAM CS# SO/ IO1 WP#/ IO2 VSS Top View VCC HOLD#/ IO3 SCLK SI/ IO0 8–LEAD VSOP/SOP 1 2 3 4 5 6 7 8 Top View 8–LEAD WSON/USON 1 2 3 4 5 6 7 8 CS# SO/ IO1 WP#/ IO2 VSS VCC HOLD#/ IO3 SCLK SI/ IO0 Pin Description of SOP8/VSOP8/USON8/WSON8 Package Pin Name Pin No. I/O Description CS# 1 I Chip Select Input SO (IO1) 2 I/O Data Output (Data Input Output 1) WP# (IO2) 3 I/O Write Protect Input (Data Input Output 2) VSS 4 Ground SI (IO0) 5 I/O Data Input (Data Input Output 0) SCLK 6 I Serial Clock Input HOLD# (IO3) 7 I/O Hold Input (Data Input Output 3) VCC 8 Power Supply Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. A2 A3 B2 B3 C2 C3 D2 D3 A1 D1 A4 D4 A2 A3 B2 B3 C2 C3 D2 D3 CS# HOLD#/ IO3 WP#/ IO2 VSS VCC SO/IO1 SCLK SI/IO0 A1 D1 A4 D4 TOP VIEW BOTTOM VIEW WLCSP (2x4 functional ball array) NC NC NC NC NC NC NC NC CS# HOLD#/ IO3 WP#/ IO2 VSS VCC SO/IO1 SCLK SI/IO0 |
Numéro de pièce similaire - GD25LE64C |
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Description similaire - GD25LE64C |
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