GD25LE05C datasheet(24/75 Pages) GIGADEVICE

No de pièce	GD25LE05C

Description	1.8V Uniform Sector Dual and Quad Serial Flash

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Fabricant	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Site Internet	http://www.gigadevice.com/

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24 / 75 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE40C/20C/10C/05C

24

Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in

accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#)

signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not

executed once the Hardware Protected Mode is entered.

Figure6. Write Status Register Sequence Diagram

7.6 Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the rising

edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency

fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single

Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure7. Read Data Bytes Sequence Diagram

7.7 Read Data Bytes at Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte

address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at

that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first

byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte

of data is shifted out.

Command

0

1

2

3

4

5

6

7

01H

CS#

SCLK

SI

SO

High-Z

8

9 10 11 12 13 14 15

MSB

7

6

5

4

3

2

1

0

Status Register in

16 17 18 19 20 21 22 23

15 14 13 12 11 10 9

8

Command

0

1

2

3

4

5

6

7

03H

CS#

SCLK

SI

SO

High-Z

8

9 10

28 29 30 31 32

MSB

3

2

1

0

34 35 36 37

33

23 22 21

7

6

5

4

3

2

1

0

38 39

24-bit address

MSB

Data Out1

Data Out2

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GD25LE05C Fiches technique(PDF) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

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