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KM736V689L Fiches technique(PDF) 8 Page - Samsung semiconductor

No de pièce KM736V689L
Description  64Kx36 Synchronous SRAM
Download  15 Pages
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Fabricant  SAMSUNG [Samsung semiconductor]
Site Internet  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM736V689L Fiches technique(HTML) 8 Page - Samsung semiconductor

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PRELIMINARY
KM736V689/L
64Kx36 Synchronous SRAM
- 8 -
Rev 1.0
April 1997
AC TIMING CHARACTERISTICS
NOTE
: 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Parameter
Symbol
-7
-8
-10
-11
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tCYC
7.5
-
8.6
-
10
-
11
-
ns
Clock Access Time
tCD
-
4.5
-
5.0
-
5.0
-
6.0
ns
Output Enable to Data Valid
tOE
-
4.5
-
5.0
-
5.0
-
6.0
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
0
-
0
-
ns
Output Hold from Clock High
tOH
1.5
-
1.5
-
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
4.0
-
4.0
-
4.0
-
4.0
ns
Clock High to Output High-Z
tHZC
1.5
5.0
1.5
5.0
1.5
5.0
1.5
5.0
ns
Clock High Pulse Width
tCH
3.0
-
3.5
-
4.0
-
4.0
-
ns
Clock Low Pulse Width
tCL
3.0
-
3.5
-
4.0
-
4.0
-
ns
Address Setup to Clock High
tAS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Status Setup to Clock High
tSS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Data Setup to Clock High
tDS
2.0
-
2.0
-
2.5
-
2.5
-
ns
Write Setup to Clock High (GW, BW, WEX)
tWS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Advance Setup to Clock High
tADVS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Chip Select Setup to Clock High
tCSS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Hold from Clock High
tAH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High (GW, BW,
tWH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
2
-
cycle
(VDD=3.3V-5%/+10%, TA=0 to 70
°C)


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