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NUC100-RE2C Datasheet(Fiches technique) 43 Page - Nuvoton Technology Corporation

Numéro de pièce NUC100-RE2C
Description  ARM® Cortex®-M 32-bit Microcontroller
Télécharger  107 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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NUC100/120xxxDN
Aug 31, 2015
Page 43 of 107
Rev 1.01
6
FUNCTIONAL DESCRIPTION
ARM
® Cortex® -M0 Core
6.1
The Cortex
® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex
® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
Cortex
® -M0
Processor
Core
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Debugger
Interface
Bus Matrix
Debug
Access
Port
(DAP)
Debug
Cortex
® -M0 processor
Cortex
® -M0 Components
Wakeup
Interrupt
Controller
(WIC)
Interrupts
Serial Wire or
JTAG Debug Port
AHB-Lite
Interface
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
ARMv6-M Thumb
® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:




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