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NUC100-VE2C Datasheet(Fiches technique) 47 Page - Nuvoton Technology Corporation

Numéro de pièce NUC100-VE2C
Description  ARM Cortex™-M0 32-BIT MICROCONTROLLER
Télécharger  89 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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 47 page
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NuMicro
™ NUC120 Data Sheet
Publication Release Date: Jan. 2, 2012
- 47 -
Revision V2.03
imer (WDT)
5.11
ows the timing of watchdog interrupt signal
and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
ter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
nable bit WTIE is
WDT
event. User must
high to reset the 18-bit WDT counter to avoid chip
T
(TRST)
ared
e reset source. WDT also
is waken up from power down state. First example, if
WTIS is set as 000, the specific time interval for chip to wake up from power down state is 2
4 *
TWDT. When power down command is set by software, then, chip enters power down state. After
2
4 * T
WDT time is elapsed, chip is waken up from power down state. Second example, if WTIS
(WDTCR [10:8]) is set as 111, the specific time interval for chip to wake up from power down
state is 2
18 * T
WDT. If power down command is set by software, then, chip enters power down
state. After 2
18 * T
WDT time is elapsed, chip is waken up from power down state. Notice if WTRE
(WDTCR [1]) is set to 1, after chip is waken up, software should clear the Watchdog Timer
counter by setting WTR(WDTCR [0]) to 1 as soon as possible. Otherwise, if the Watchdog Timer
counter is not cleared by setting WTR (WDTCR [0]) to 1 before time starting from waking up to
software clearing Watchdog Timer counter is over 1024 * TWDT , the chip is reset by Watchdog
Timer.
5.11 Watchdog T
.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wake-up chip from power down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals. Table 5-5 show the
watchdog timeout interval selection and Figure 5-64 sh
When the coun
be set immediately to request a WDT interrupt if the watchdog timer interrupt e
4 * T
) follows the time-out
set, in the meanwhile, a specified delay time (102
set WTR (WDTCR [0]) (Watchdog timer reset)
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WD
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset chip. This reset will last 63 WDT clocks
then chip restarts executing program from reset vector (0x0000_0000). WTRF will not be cle
by Watchdog reset. User may poll WTRF by software to recognize th
provides wake-up function. When chip is powered down and the Watchdog Timer Wake-up
Function Enable bit (WDTR[4]) is set, if the WDT counter reaches the specific time interval
defined by WTIS (WDTCR [10:8]) , the chip
WTIS
Timeout Interval
Selection
TTIS
Interrupt Period
TINT
WTR Timeout Interval
(WDT_CLK=10 kHz)
Min. TWTR ~ Max. TWTR
000
2
4 * TWDT
1024 * TWDT
1.6 ms ~ 104 ms
001
2
6 * TWDT
1024 * TWDT
6.4 ms ~ 108.8 ms
010
2
8 * TWDT
1024 * TWDT
25.6 ms ~ 128 ms
011
2
10 * TWDT
1024 * TWDT
102.4 ms ~ 204.8 ms
100
2
12 * TWDT
1024 * TWDT
409.6 ms ~ 512 ms
101
2
14 * TWDT
1024 * TWDT
1.6384 s ~ 1.7408 s
110
2
16 * TWDT
1024 * TWDT
6.5536 s ~ 6.656 s
111
2
18 * TWDT
1024 * TWDT
26.2144 s ~ 26.3168 s
Table 5-5 Watchdog Timeout Interval Selection




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