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GPC71P080A Datasheet(Fiches technique) 7 Page - Generalplus Technology Inc.

Numéro de pièce GPC71P080A
Description  4-bit Speech with SPU
Télécharger  19 Pages
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Fabricant  GENERALPLUS [Generalplus Technology Inc.]
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© Generalplus Technology Inc.
Proprietary & Confidential
Dec. 20, 2016
Version: 1.2
7.1 CPU
GPC71PXXXA features a 4-bit RISC CPU, executing the 12-bit
instruction set with total of 72 instructions available, 7 stacks
managed by a 3-bit stack pointer, three DPRs(Data Pointer to
read ROM) sharing stack 4 ~ 6, and two VPRs(Voice Data Pointer)
for SPU.
7.2 Memory
7.2.1 SRAM
There are 256 nibbles of SRAM, grouped into 4 banks.
bank has 64 nibbles and supports index mode to read/write its
content addressed by TXR.
7.2.2 OTP
The One Time Programming (OTP) memory is featured in
GPC71PXXXA with density of 680K/ 340K/ 160K/ 128K/ 96K/
64K/ 32K x 12-bit of memory.
7.3 Clock Source
Clock source is an inner resistance oscillator with CPU clock
options of 1MHz or 2MHz
7.4 Low Voltage Reset
With the LVR function, a reset signal is generated to reset system
when the operating voltage drops below LVR level.
7.5 Interrupt
An interrupt is a special event request to microcontroller.
it occurs, the corresponding interrupt will activate and direct the
program code to execute the respective functions.
GPC71PXXXA has 5 interrupt sources.
Please refer to
programming guide for more details.
7.5.1 Timebase
There are two Timebases, TB1 and TB2, generated by the system
The interval of TB1 is allowed up to 1ms and TB2 allows
up to 2ms.
7.6 SPU
One channel SPU supports MIDI playback with A3400Pro-like
decode or PCM format, and each channel has an 8-bit envelope
7.7 PWM
The PWM module consists of a 14-bit PWM driver to drive
speaker directly.
7.8 Sleep Mode, Wakeup and Watchdog
7.8.1 Sleep mode and wakeup
Sleep mode or known as power down mode is an operating state
that requires an extremely low power consumption to maintain the
system in active.
The sleep mode is particularly useful for the
application areas where the system is required to constantly
maintain its basic functionality and where the power capacity is
GPC71PXXXA enters sleep mode when SLEEP
instruction is executed and can be woken up by interrupt or key
state change.
CPU will continue to execute the rest of program
code from where it entered sleep mode.
7.8.2 Watchdog Reset
A watchdog reset is a reset signal that is generated to reset the
entire system when watchdog counter is overflow.
In case when
the program code has been running into an unknown state and
without the watchdog signal being cleared for a certain period of
time, watchdog function automatically generates a reset signal
pulling the system back from unknown state.
7.9 . I/O
The GPC71PXXXA features 16-bit or 8-bit programmable
Input/output pins and many of them feature wakeup capability.
These IOs normally support input function with floating or pull-low
and output options.
In addition to the ordinary I/O function, some
IO ports have special functions.
The following table summarizes
the special functions for these IOs.
Special Function in Port
Special Function
Function Description
Key Reset
Key reset pin, configurable through code option
High active; IOC0/IOD0 isn
’t supported
in GPC71P032A/GPC71P016A
IR carry output, configurable through code option
IOC1/IOD1 isn
’t supported in
External interrupt input, configurable through code option
IOC2/IOD2 isn
’t supported in

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