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NUC120-YC3E Fiches technique(PDF) 69 Page - Nuvoton Technology Corporation |
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NUC120-YC3E Fiches technique(HTML) 69 Page - Nuvoton Technology Corporation |
69 / 107 page NUC100/120xxxDN Aug 31, 2015 Page 69 of 107 Rev 1.01 PDMA Controller (PDMA) 6.7 6.7.1 Overview The NuMicro ® NUC100 series DMA contains nine-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA that transfers data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA PDMA_CSRx[PDMACEN]. The CPU can recognize the completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller can increase source or destination address or fixed them as well. The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode and DMA transfer mode. 6.7.2 Features Supports nine PDMA channels and one CRC channel. Each PDMA channel can support a unidirectional transfer AMBA AHB master/slave interface compatible, for data transfer and register read/write Hardware round robin priority scheme. DMA channel 0 has the highest priority and channel 8 has the lowest priority PDMA operation – Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer – Supports word/half-word/byte transfer data width from/to peripheral – Supports address direction: increment, fixed. Cyclic Redundancy Check (CRC) – Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 CRC-CCITT: X 16 + X12 + X5 + 1 CRC-8: X 8 + X2 + X + 1 CRC-16: X 16 + X15 + X2 + 1 CRC-32: X 32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 – Supports programmable CRC seed value. – Supports programmable order reverse setting for input data and CRC checksum. – Supports programmable 1’s complement setting for input data and CRC checksum. – Supports CPU PIO mode or DMA transfer mode. – Supports the follows write data length in CPU PIO mode 8-bit write mode (byte): 1-AHB clock cycle operation. 16-bit write mode (half-word): 2-AHB clock cycle operation. 32-bit write mode (word): 4-AHB clock cycle operation. – Supports byte alignment transfer data length and word alignment transfer source address in CRC DMA mode. |
Numéro de pièce similaire - NUC120-YC3E |
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Description similaire - NUC120-YC3E |
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