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NUC100-YA3E Fiches technique(PDF) 48 Page - Nuvoton Technology Corporation |
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NUC100-YA3E Fiches technique(HTML) 48 Page - Nuvoton Technology Corporation |
48 / 107 page NUC100/120xxxDN Aug 31, 2015 Page 48 of 107 Rev 1.01 nRESET Reset 6.2.2.1 The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6-3 shows the nRESET reset waveform. SS nRESET 0.2 VDD 0.7 VDD nRESET Reset SS 36 us 36 us Figure 6-3 nRESET Reset Waveform Power-On Reset (POR) 6.2.2.2 The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset. VDD VPOR Power On Reset 0.1V Figure 6-4 Power-on Reset (POR) Waveform Low Voltage Reset (LVR) 6.2.2.3 If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD during system operation. When the |
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