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NUC220-RD2E Fiches technique(PDF) 59 Page - Nuvoton Technology Corporation |
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NUC220-RD2E Fiches technique(HTML) 59 Page - Nuvoton Technology Corporation |
59 / 107 page NUC100/120xxxDN Aug 31, 2015 Page 59 of 107 Rev 1.01 6.2.7 Nested Vectored Interrupt Controller (NVIC) The Cortex ® -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features: Nested and Vectored interrupt support Automatic processor state saving and restoration Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processo r state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also support s “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the “ARM ® Cortex® -M0 Technical Reference Manual” and “ARM ® v6-M Architecture Reference Manual”. |
Numéro de pièce similaire - NUC220-RD2E |
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