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NUC230-YE3N Datasheet(Fiches technique) 63 Page - Nuvoton Technology Corporation

Numéro de pièce NUC230-YE3N
Description  ARM® Cortex®-M 32-bit Microcontroller
Télécharger  107 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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 63 page
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NUC100/120xxxDN
Aug 31, 2015
Page 63 of 107
Rev 1.01
6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-12.
111
011
010
001
PLLFOUT
32.768 kHz
4~24 MHz
10 kHz
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
000
1/(HCLK_N+1)
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
CPU
AHB
APB
CPUCLK
HCLK
PCLK
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-12 System Clock Block Diagram
The clock source of SysTick in Cortex
® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-13.
111
011
010
001
4~24 MHz
32.768 kHz
4~24 MHz
HCLK
STCLK_S (CLKSEL0[5:3])
STCLK
22.1184 MHz
000
1/2
1/2
1/2
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-13 SysTick Clock Control Block Diagram




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