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NUC140-VC3C Fiches technique(PDF) 73 Page - Nuvoton Technology Corporation

No de pièce NUC140-VC3C
Description  NuMicro
Download  97 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC140-VC3C Fiches technique(HTML) 73 Page - Nuvoton Technology Corporation

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NuMicro NUC230/240 Datasheet
Dec. 30, 2014
Page 73 of 97
Revision 1.01
6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal. It also
support UART mode for full duplex asynchronous communications.
6.14.2 Features
Supports up to three ISO7816-3 ports (SC0, SC1 and SC2)
-
ISO7816-3 T=0, T=1 compliant
-
EMV2000 compliant
-
Separates receive/ transmit 4 byte entry FIFO for data payloads.
-
Programmable transmission clock frequency.
-
Programmable receiver buffer trigger level.
-
Programmable guard time selection (11 ETU ~ 267 ETU).
-
A 24-bit and two 8-bit times for Answer to Request (ATR) and waiting times
processing.
-
Supports auto inverse convention function.
-
Supports transmitter and receiver error retry and error number limiting function.
-
Supports hardware activation sequence, hardware warm reset sequence and
hardware deactivation sequence process.
-
Supports hardware auto deactivation sequence when detecting the card
removal.
Supports up to three UART ports (UART3, UART4, UART5)
-
Full duplex, asynchronous communications.
-
Programmable data bit length, 5-, 6-, 7-, 8-bit character.
-
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
-
Supports programmable baud rate generator for each channel.
-
Supports programmable receiver buffer trigger level.
-
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register.
-
Programmable even, odd or no parity bit generation and detection.
-
Programmable stop bit, 1 or 2 stop bit generation.


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