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NUC140-YB2N Datasheet(Fiches technique) 38 Page - Nuvoton Technology Corporation

Numéro de pièce NUC140-YB2N
Description  ARM Cortex™-M0 32-BIT MICROCONTROLLER
Télécharger  89 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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 38 page
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NuMicro
™ NUC120 Data Sheet
Publication Release Date: Jan. 2, 2012
- 38 -
Revision V2.03
)
5.4.
nterrupt/
USB bus which comes
starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this de
(USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Reference: Universal Serial Bus Specification Revision 1.1
5.4.2
Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
Compliant with USB 2.0 Full-Speed specification
Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Support Control/Bulk/Interrupt/Isochronous transfer type
Support suspend function when no bus activity existing for 3 ms
Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 bytes buffer size
Provide remo
5.4
USB Device Controller (USB
1
Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and support control/bulk/i
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE.
Users need to set the effective
vice from the host. If user enables DRVSE0 bit
te wake-up capability




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