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NUC120-YB2N Fiches technique(PDF) 35 Page - Nuvoton Technology Corporation |
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NUC120-YB2N Fiches technique(HTML) 35 Page - Nuvoton Technology Corporation |
35 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 35 - Revision V2.03 ysTick Clock ock generator block. The (CLKSEL0[2:0]). The block diagram is 5.3.3 System Clock and S The system clock has 5 clock sources which were generated from cl clock source switch depends on the register HCLK_S showed in Figure 5-5. 111 011 010 001 PLLFOUT 32.768 kHz 4~24 MHz 10 kHz HCLK_S (CLKSEL0[2:0]) 22.1184 MHz 000 1/(HCLK_N+1) HCLK_N (CLKDIV[3:0]) CPU in Power Down Mode CPU AHB CPUCLK HCLK PCLK APB Figure 5-5 System Clock Block Diagram The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is showed in Figure 5-6. Fig m ure 5-6 SysTick Clock Control Block Diagra |
Numéro de pièce similaire - NUC120-YB2N |
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