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NUC130-LC2C Datasheet(Fiches technique) 15 Page - Nuvoton Technology Corporation

Numéro de pièce NUC130-LC2C
Description  NuMicro
Télécharger  97 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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 15 page
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NuMicro NUC230/240 Datasheet
Dec. 30, 2014
Page 15 of 97
Revision 1.01
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in Slave
mode
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
 I
2C
Up to two sets of I
2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
 I
2S
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I
2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
 PS/2 Device
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
 CAN 2.0
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Object)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Supports Power-down wake-up function
 USB 2.0 Full-Speed Device
One set of USB 2.0 FS Device 12 Mbps
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer




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