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NUC130-LC2C Fiches technique(PDF) 14 Page - Nuvoton Technology Corporation

No de pièce NUC130-LC2C
Description  NuMicro
Download  97 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC130-LC2C Fiches technique(HTML) 14 Page - Nuvoton Technology Corporation

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NuMicro NUC230/240 Datasheet
Dec. 30, 2014
Page 14 of 97
Revision 1.01
 Window Watchdog Timer
6-bit down counter with 11-bit prescale for wide range window selected
 RTC
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4,
1/2 and 1 second
Supports battery power pin (VBAT)
Supports wake-up function
 PWM/Capture
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM
Supports One-shot or Auto-reload mode
Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
Supports Capture interrupt
 UART
Up to six UART controllers (three UART controllers are shared with SC)
UART ports with flow control (TXD, RXD, nCTS and nRTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports CTS wake-up function (UART0 and UART1 support)
Supports PDMA mode
 Smart Card Host (SC)
Supports up to three ISO-7816-3 ports
 Compliant to ISO-7816-3 T=0, T=1
 Separate receive / transmit 4 bytes entry FIFO for data payloads
 Programmable transmission clock frequency
 Programmable receiver buffer trigger level
 Programmable guard time selection (11 ETU ~ 266 ETU)
 One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
 Supports auto inverse convention function
 Supports transmitter and receiver error retry and error limit function
 Supports hardware activation sequence process
 Supports hardware warm reset sequence process
 Supports hardware deactivation sequence process
 Supports hardware auto deactivation sequence when detecting the card is removal
Supports up to three UART ports
 Full duplex, asynchronous communications
 Supports receiving / transmitting 4-bytes FIFO
 Supports programmable baud rate generator for each channel
 Programmable even, odd or no parity bit generation and detection
 Programmable stop bit, 1 or 2 stop bit generation
 SPI
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)


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