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NUC130-LC2C Fiches technique(PDF) 75 Page - Nuvoton Technology Corporation

No de pièce NUC130-LC2C
Description  NuMicro
Download  97 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC130-LC2C Fiches technique(HTML) 75 Page - Nuvoton Technology Corporation

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NuMicro NUC230/240 Datasheet
Dec. 30, 2014
Page 75 of 97
Revision 1.01
6.16 I
2C Serial Interface Controller (I2C)
6.16.1 Overview
I
2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I
2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
6.16.2 Features
The I
2C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices
connected to the bus. The main features of the I
2C bus include:
Supports up to two I
2C serial interface controller
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in a 14-bit time-out counter requesting the I
2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
6.17 Serial Peripheral Interface (SPI)
6.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro
 NUC230/240 series contains up to four sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable bus clock function for special applications and 2-bit
Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports
the PDMA function to access the data buffer and also supports Dual I/O Transfer mode.


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