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NUC130-LC2C Fiches technique(PDF) 57 Page - Nuvoton Technology Corporation |
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NUC130-LC2C Fiches technique(HTML) 57 Page - Nuvoton Technology Corporation |
57 / 97 page NuMicro NUC230/240 Datasheet Dec. 30, 2014 Page 57 of 97 Revision 1.01 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex™-M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the overall system power consumption. The following figures show the clock generator and the overview of the clock source control. The clock generator consists of 5 clock sources as listed below: 32.768 kHz external low speed crystal oscillator (LXT) 4~24 MHz external high speed crystal oscillator (HXT) Programmable PLL output clock frequency (PLL source can be selected from external 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high speed RC oscillator (HIRC)) (PLL FOUT) 22.1184 MHz internal high speed RC oscillator (HIRC) 10 kHz internal low speed RC oscillator (LIRC) |
Numéro de pièce similaire - NUC130-LC2C |
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Description similaire - NUC130-LC2C |
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