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NUC130-LC2C Fiches technique(PDF) 56 Page - Nuvoton Technology Corporation |
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NUC130-LC2C Fiches technique(HTML) 56 Page - Nuvoton Technology Corporation |
56 / 97 page NuMicro NUC230/240 Datasheet Dec. 30, 2014 Page 56 of 97 Revision 1.01 6.2.6.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset Description 0 SP_main – The Main stack pointer Vector Number Exception Entry Pointer using that Vector Number Table 6-4 Vector Table Format 6.2.6.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set- Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. 6.2.7 System Control The Cortex™-M0 status and operating mode control are managed by System Control Registers. Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be controlled through these system control registers. For more detailed information, please refer to the “ARM ® Cortex™-M0 Technical Reference Manual” and “ARM ® v6-M Architecture Reference Manual”. |
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