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NUC220-LE1N Fiches technique(PDF) 11 Page - Nuvoton Technology Corporation

No de pièce NUC220-LE1N
Description  ARM짰 Cortex짰-M 32-bit Microcontroller
Download  107 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC220-LE1N Fiches technique(HTML) 11 Page - Nuvoton Technology Corporation

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NUC100/120xxxDN
Aug 31, 2015
Page 11 of 107
Rev 1.01
Supports three wire, no slave select signal, bi-direction interface
I
2C
Up to two sets of I
2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
I
2S
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I
2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
EBI (External bus interface)
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
ADC
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Supports PDMA mode
Analog Comparator
Up to two analog comparators
External input or internal Band-gap voltage selectable at negative node
Interrupt when compare results change
Supports Power-down wake-up
Smart Card Host (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports


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