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NUC220-LE1N Fiches technique(PDF) 68 Page - Nuvoton Technology Corporation

No de pièce NUC220-LE1N
Description  ARM짰 Cortex짰-M 32-bit Microcontroller
Download  107 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC220-LE1N Fiches technique(HTML) 68 Page - Nuvoton Technology Corporation

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NUC100/120xxxDN
Aug 31, 2015
Page 68 of 107
Rev 1.01
General Purpose I/O (GPIO)
6.6
6.6.1
Overview
The NuMicro
® NUC100 series has up to 84 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named
as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the
maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 84 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K
 for V
DD is from 5.0 V to 2.5 V.
6.6.2
Features
Four I/O modes:
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.


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