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NUC120-RB1N Fiches technique(PDF) 32 Page - Nuvoton Technology Corporation |
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NUC120-RB1N Fiches technique(HTML) 32 Page - Nuvoton Technology Corporation |
32 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 32 - Revision V2.03 ler 5.3. ets the power down enable bit (PWR_DOWN_EN) and Cortex-M0 core executes the WFI instruction. After that, chip enter power down mode and wait for wake-up interrupt source triggered to leave power down mode. In the power down mode, the c e 24 MHz high speed crystal and internal 22.1184 MHz high speed oscilla r to reduce t ption. 5.3 Clock Control 1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter power down mode until CPU s lock controller turns off th external 4~ to he overall system power consum |
Numéro de pièce similaire - NUC120-RB1N |
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Description similaire - NUC120-RB1N |
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