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NUC140-VE2N Datasheet(Fiches technique) 77 Page - Nuvoton Technology Corporation

Numéro de pièce NUC140-VE2N
Description  NuMicro
Télécharger  97 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
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 77 page
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NuMicro NUC230/240 Datasheet
Dec. 30, 2014
Page 77 of 97
Revision 1.01
6.19 USB Device Controller (USBD)
6.19.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs
to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of
“Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, and BUS events. Any event will cause an interrupt, and
users just need to check the related event flags in interrupt event status register (USB_INTSTS)
to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status
Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If DRVSE0 (USB_DRVSE0[0]) is set to 1, the USB
controller will force the output of USB_D+ and USB_D- to level low. After DRVSE0 bit is cleared
to 0, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1 for details.
6.19.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability




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