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NUC100RD1DN Fiches technique(PDF) 15 Page - Nuvoton Technology Corporation |
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NUC100RD1DN Fiches technique(HTML) 15 Page - Nuvoton Technology Corporation |
15 / 107 page NUC100/120xxxDN Aug 31, 2015 Page 15 of 107 Rev 1.01 – Up to two sets of I 2C device – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function I 2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I 2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus EBI (External bus interface) – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode USB 2.0 Full-Speed Device – One set of USB 2.0 FS Device 12 Mbps – On-chip USB Transceiver – Provides 1 interrupt source with 4 interrupt events – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers – Auto suspend function when no bus signaling for 3 ms – Provides 6 programmable endpoints – Includes 512 Bytes internal SRAM as USB buffer – Provides remote wake-up capability ADC – 12-bit SAR ADC with 760 kSPS – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming or external input – Supports PDMA mode Analog Comparator |
Numéro de pièce similaire - NUC100RD1DN |
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Description similaire - NUC100RD1DN |
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