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NAU8502YG Fiches technique(PDF) 57 Page - Nuvoton Technology Corporation |
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NAU8502YG Fiches technique(HTML) 57 Page - Nuvoton Technology Corporation |
57 / 92 page NAU8502 emPowerAudio ™ Datasheet Revision 2.5 Page 57 of 92 March, 2014 12 REGISTER DESCRIPTION There are two dedicated register spaces: 8737 space 0x00 to 0x0F and 0x1C NAU8502 space from 0x21 and on The NAU8502 register map have a reserved space from register 0x00 to register 0x0F and 0x1C that mimic the 8737 registers.. Programming in this address space [0x00-0x0F:0x1C] will trigger the appropriate functions in the NAU8502 via mapping. Register Address Register Bits Default DEC HEX D8 D7 D6 D5 D4 D3 D2 D1 D0 PGA volume 0 0 LVU LINVOL C3 1 1 RVU RINVOL C3 Audio path 2 2 LMICBOOST LMBE LMZC LPZC 07 3 3 RMICBOOST RMBE RMZC RPZC 07 3D 4 4 00 ADC control 5 5 POLARITY 0 LP ADC HPD 00 Power Management 6 6 VMID VREF AI PGL PGR ADL ADR MICBIAS 80 Audio Format and clocking 7 7 SDODIS MS FSP WLEN FORMAT 0A 8 8 CLKDIV2 SR 00 Mic pre-amp and bias 9 9 MBCTRL 0F 10 A VMIDSEL LIN DC EN RIN DC EN 03 Noise gate and ALC 11 B ALCMINGAIN NGTH NGAT 00 12 C ALCEN ALCMAXGAIN ALCSL 7C 13 D ALCMODE ALCZCE HLD 00 14 E DCY ATK 32 Reset 15 F Software Reset 00 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A 27 1B 28 1C 4 29 1D 30 1E 31 1F 32 20 Power management 33 21 BIASEN BUFIOEN 00 Audio path selection 34 22 LLINOUTEN RLINOUTEN SLEEP VINSEL LMICN2BVREF RMICN2BVREF 00 Register Address Register Bits Default |
Numéro de pièce similaire - NAU8502YG |
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